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ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
14 years 6 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
RTA
2010
Springer
14 years 1 months ago
Certified Subterm Criterion and Certified Usable Rules
Abstract. In this paper we present our formalization of two important termination techniques for term rewrite systems: the subterm criterion and the reduction pair processor in com...
Christian Sternagel, René Thiemann
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
13 years 11 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
CGF
2005
232views more  CGF 2005»
13 years 9 months ago
Algorithms for Interactive Editing of Level Set Models
Level set models combine a low-level volumetric representation, the mathematics of deformable implicit surfaces, and powerful, robust numerical techniques to produce a novel appro...
Ken Museth, David E. Breen, Ross T. Whitaker, Sean...
UIST
2004
ACM
14 years 2 months ago
Hierarchical parsing and recognition of hand-sketched diagrams
A long standing challenge in pen-based computer interaction is the ability to make sense of informal sketches. A main difficulty lies in reliably extracting and recognizing the i...
Levent Burak Kara, Thomas F. Stahovich