118 search results - page 6 / 24 » Analysis and Minimization of Test Time in a Combined BIST an... |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
ETS
2007
IEEE
13 years 8 months ago
2007
IEEE
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
ICDAR
2009
IEEE
14 years 1 months ago
2009
IEEE
Classifier combination is a powerful strategy to support useful solutions in difficult classification problems. Notwithstanding, the effectiveness of a multi-classifier system str...
VTS
2002
IEEE
13 years 11 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
ICASSP
2011
IEEE
12 years 10 months ago
2011
IEEE
In this paper we introduce a new technique for estimating the parameters of the Keplerian model commonly used in radial velocity data analysis for extrasolar planet detection. The...