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ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 10 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
DAC
2008
ACM
14 years 10 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
RTSS
2003
IEEE
14 years 2 months ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
ACL
1998
13 years 10 months ago
Part of Speech Tagging Using a Network of Linear Separators
We present an architecture and an on-line learning algorithm and apply it to the problem of part-ofspeech tagging. The architecture presented, SNOW, is a network of linear separat...
Dan Roth, Dmitry Zelenko
HPCA
2007
IEEE
14 years 9 months ago
Exploiting Postdominance for Speculative Parallelization
Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam...