Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Current IT application domains such as web services and autonomic computing call for highly flexible systems, able to automatically adapt to changing operational environments as w...
Loris Penserini, Anna Perini, Angelo Susi, John My...