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DAC
2006
ACM
14 years 10 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
IPPS
2000
IEEE
14 years 1 months ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou
ICS
2009
Tsinghua U.
14 years 1 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
EMSOFT
2007
Springer
14 years 3 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
EUMAS
2006
13 years 10 months ago
Agent Capability: Automating the Design to Code Process
Current IT application domains such as web services and autonomic computing call for highly flexible systems, able to automatically adapt to changing operational environments as w...
Loris Penserini, Anna Perini, Angelo Susi, John My...