Criticality computation in parameterized statistical timing

Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids; B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Algorithms, Verification Keywords Criti...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
• Keywords: Criticality Computation, DAC 2006, Design Automation, Keywords Criticality Probability, Large Parametric Variations