38 search results - page 3 / 8 » Analysis and approximation of optimal co-scheduling on chip ... |
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
ICS
1999
Tsinghua U.
14 years 5 days ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
ITNG
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
ICPPW
2008
IEEE
14 years 2 months ago
2008
IEEE
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....