Sciweavers

8 search results - page 2 / 2
» Analysis and optimization of NBTI induced clock skew in gate...
Sort
View
ISCAS
2008
IEEE
132views Hardware» more  ISCAS 2008»
14 years 2 months ago
Thermal aware clock synthesis considering stochastic variation and correlations
— In this paper, we have proposed a thermal aware routing based parameterization to generate a clock model that takes the stochastic temperature variation into consideration. The...
Chunchen Liu, Ruei-Xi Chen, Jichang Tan, Sharon Fa...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 1 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 2 months ago
Use of statistical timing analysis on real designs
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gr...