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VLSISP
2008
123views more  VLSISP 2008»
13 years 7 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 2 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 1 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
VLSISP
2008
239views more  VLSISP 2008»
13 years 7 months ago
An Embedded Real-Time Surveillance System: Implementation and Evaluation
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...