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DAC
2012
ACM
11 years 10 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
ISCA
2005
IEEE
87views Hardware» more  ISCA 2005»
14 years 1 months ago
A Robust Main-Memory Compression Scheme
Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The propose...
Magnus Ekman, Per Stenström
HPCC
2007
Springer
14 years 1 months ago
A Block JRS Algorithm for Highly Parallel Computation of SVDs
This paper presents a new algorithm for computing the singular value decomposition (SVD) on multilevel memory hierarchy architectures. This algorithm is based on one-sided JRS iter...
Mostafa I. Soliman, Sanguthevar Rajasekaran, Reda ...
CIDR
2007
144views Algorithms» more  CIDR 2007»
13 years 9 months ago
Cache-Oblivious Query Processing
We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...
Bingsheng He, Qiong Luo
USENIX
2007
13 years 10 months ago
DiskSeen: Exploiting Disk Layout and Access History to Enhance I/O Prefetch
Current disk prefetch policies in major operating systems track access patterns at the level of the file abstraction. While this is useful for exploiting application-level access...
Xiaoning Ding, Song Jiang, Feng Chen, Kei Davis, X...