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ASPLOS
1989
ACM
13 years 11 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
IPPS
2006
IEEE
14 years 1 months ago
Performance Analysis of the Reactor Pattern in Network Services
The growing reliance on services provided by software applications places a high premium on the reliable and efficient operation of these applications. A number of these applicat...
Swapna S. Gokhale, Aniruddha S. Gokhale, Jeffrey G...
EDOC
2007
IEEE
14 years 1 months ago
Modeling and Integrating Aspects into Component Architectures
Dependable software systems are difficult to develop because developers must understand and address several interdependent and pervasive dependability concerns. Features that addr...
Lydia Michotte, Robert B. France, Franck Fleurey
HPCA
2007
IEEE
14 years 8 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
ICS
2007
Tsinghua U.
14 years 1 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev