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MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 10 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
15 years 10 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
PIMRC
2008
IEEE
15 years 10 months ago
Connection admission control and grade of service for QoS routing in mesh networks
—Wireless mesh networks (WMNs) is a promising key technology for next generation wireless backhauling that have recently attracted both the academic and industrial interest. Such...
Chi Harold Liu, Athanasios Gkelias, Kin K. Leung
BROADNETS
2007
IEEE
15 years 10 months ago
Reduced flow routing: Leveraging residual capacity to reduce blocking in GMPLS networks
— Traffic engineering has been extensively studied to maximize network resource utilization while minimizing call blocking [1]. As the the demand for high data rate services ove...
Xiaolan J. Zhang, Sun-il Kim, Steven S. Lumetta
CODES
2007
IEEE
15 years 10 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer