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ICS
2009
Tsinghua U.
13 years 12 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
BMCBI
2010
96views more  BMCBI 2010»
13 years 7 months ago
ChIPpeakAnno: a Bioconductor package to annotate ChIP-seq and ChIP-chip data
Background: Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) or ChIP followed by genome tiling array analysis (ChIP-chip) have become standar...
Lihua J. Zhu, Claude Gazin, Nathan D. Lawson, Herv...
HPCA
2005
IEEE
14 years 7 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...
CCGRID
2006
IEEE
14 years 1 months ago
GRENCHMARK: A Framework for Analyzing, Testing, and Comparing Grids
Grid computing is becoming the natural way to aggregate and share large sets of heterogeneous resources. With the infrastructure becoming ready for the challenge, current grid dev...
Alexandru Iosup, Dick H. J. Epema
IEEEPACT
2006
IEEE
14 years 1 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...