32 search results - page 3 / 7 » Analysis of SEU Effects in a Pipelined Processor |
RTSS
2003
IEEE
14 years 22 days ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
The emergence of multicore processors has heightened the need for effective parallel programming practices. In addition to writing new parallel programs, the next generation of pr...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
JILP
2000
13 years 7 months ago
2000
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
EXPCS
2007
13 years 9 months ago
2007
Pipeline Spectroscopy is a new technique that allows us to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogram, which represents a precis...