132 search results - page 8 / 27 » Analysis of Shared Memory Misses and Reference Patterns |
ANSS
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we present simulation algorithmsthat characterize the main sources of communication generated by parallel applications under both invalidate and updatebased cache co...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very ...
ISPASS
2008
IEEE
14 years 1 months ago
2008
IEEE
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
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ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical me...
CF
2009
ACM
14 years 2 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...