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MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 26 days ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
CODES
2008
IEEE
14 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
LCTRTS
2004
Springer
14 years 28 days ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
FLAIRS
2004
13 years 9 months ago
An Active Architecture for Managing Events in Pervasive Computing Environments
Many dramatizations have depicted a fully automated home living environment, where actions and events are understood or even anticipated. While the realization of such environment...
Edwin Wong, Lisa J. Burnell, Charles Hannon
DAC
2010
ACM
13 years 11 months ago
On the costs and benefits of stochasticity in stream processing
With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of onchip ...
Raj R. Nadakuditi, Igor L. Markov