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» Analysis of a reconfigurable network processor
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ARC
2010
Springer
186views Hardware» more  ARC 2010»
13 years 11 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
ICT
2004
Springer
131views Communications» more  ICT 2004»
14 years 1 months ago
Fairness and Protection Behavior of Resilient Packet Ring Nodes Using Network Processors
The Resilient Packet Ring IEEE 802.17 is an evolving standard for the construction of Local and Metropolitan Area Networks. The RPR protocol scales to the demands of future packet ...
Andreas Kirstädter, Axel Hof, Walter Meyer, E...
AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 1 months ago
A Generic On-Chip Debugger for Wireless Sensor Networks
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier
DATE
2002
IEEE
115views Hardware» more  DATE 2002»
14 years 21 days ago
Design Technology for Networked Reconfigurable FPGA Platforms
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
Steve Guccione, Diederik Verkest, Ivo Bolsens
CODES
2005
IEEE
14 years 1 months ago
FlexPath NP: a network processor concept with application-driven flexible processing paths
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild