65 search results - page 4 / 13 » Analysis of buffered hybrid structured clock networks |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
HPCA
1998
IEEE
14 years 55 sec ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
ISQED
2002
IEEE
14 years 19 days ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, ...
SIGMETRICS
1990
ACM
13 years 11 months ago
1990
ACM
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...