747 search results - page 16 / 150 » Analysis of communication delay bounds for network on chips |
INFOCOM
1992
IEEE
14 years 1 months ago
1992
IEEE
This paper describes a methodology for designing interconnected LAN-MAN networks with the objective of minimizing the average network delay. We consider IEEE 802.3-5 LANs intercon...
CDC
2008
IEEE
14 years 3 months ago
2008
IEEE
— This paper studies the problem of stability analysis for neural networks (NNs) with a time-varying delay. The activation functions are assumed to be neither monotonic, nor diff...
SDL
2003
13 years 10 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
ICCAD
2000
IEEE
14 years 1 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
CASES
2006
ACM
14 years 3 months ago
2006
ACM
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...