747 search results - page 7 / 150 » Analysis of communication delay bounds for network on chips |
INFOCOM
1991
IEEE
13 years 11 months ago
1991
IEEE
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—We propose (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communicat...
VTC
2008
IEEE
14 years 2 months ago
2008
IEEE
–In this paper we present an analytical model for delay tolerant message propagation in a dynamic vehicular network. The analysis provides upper and lower bounds for message prop...
INFOCOM
2011
IEEE
12 years 11 months ago
2011
IEEE
Abstract—In this paper, we provide an analysis of the information propagation speed in bidirectional vehicular delay tolerant networks on highways. We show that a phase transitio...