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» Analysis of power consumption in memory hierarchies
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WH
2010
171views Healthcare» more  WH 2010»
13 years 2 months ago
Evaluation of body sensor network platforms: a design space and benchmarking analysis
Body Sensor Networks (BSNs) consist of sensor nodes deployed on the human body for health monitoring. Each sensor node is implemented by interfacing a physiological sensor with a ...
Sidharth Nabar, Ayan Banerjee, Sandeep K. S. Gupta...
ISPAN
2000
IEEE
13 years 12 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
CODES
2008
IEEE
14 years 2 months ago
Cache-aware optimization of BAN applications
Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring ...
Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mi...
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
14 years 1 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
HPCA
2004
IEEE
14 years 7 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...