Sciweavers

99 search results - page 8 / 20
» Analysis of power consumption in memory hierarchies
Sort
View
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 11 months ago
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
In data dominated applications, like multi-media and telecom applications, data storage and transfers are the most important factors in terms of energy consumption, area and syste...
Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytac...
IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 1 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
ICNP
2003
IEEE
14 years 25 days ago
Packet Classification Using Extended TCAMs
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
Ed Spitznagel, David E. Taylor, Jonathan S. Turner
ICPPW
2002
IEEE
14 years 14 days ago
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
Jaume Abella, Antonio González, Josep Llosa...
IPCCC
2007
IEEE
14 years 1 months ago
Optimal Cluster Head Selection in the LEACH Architecture
LEACH (Low Energy Adaptive Clustering Hierarchy) [1] is one of the popular cluster-based structures, which has been widely proposed in wireless sensor networks. LEACH uses a TDMA ...
Haiming Yang, Biplab Sikdar