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SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
14 years 18 days ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager
ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
14 years 1 months ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...
IPPS
2007
IEEE
14 years 2 months ago
Improving Scalability of OpenMP Applications on Multi-core Systems Using Large Page Support
Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the...
Ranjit Noronha, Dhabaleswar K. Panda
ANSS
2007
IEEE
13 years 10 months ago
Modelling Network Memory Servers with Parallel Processors, Break-downs and Repairs
This paper presents an analytical method for the performability evaluation of a previously reported network memory server attached to a local area network. To increase the perform...
Orhan Gemikonakli, Glenford E. Mapp, Enver Ever, D...
HPCA
2007
IEEE
14 years 9 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...