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ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
13 years 11 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
SPAA
2003
ACM
14 years 21 days ago
Quantifying instruction criticality for shared memory multiprocessors
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed...
Tong Li, Alvin R. Lebeck, Daniel J. Sorin
ISCA
2005
IEEE
154views Hardware» more  ISCA 2005»
14 years 1 months ago
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Tempor...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...
SPAA
2010
ACM
14 years 8 days ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha
DSD
2002
IEEE
146views Hardware» more  DSD 2002»
14 years 12 days ago
Configurable Memory Organisation for Communication Applications
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...
Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivain...