98 search results - page 9 / 20 » Analytic Evaluation of Shared-memory Systems with ILP Proces... |
IPL
1998
13 years 8 months ago
1998
We propose, and justify, an economic theory to guide memory system design, operation, and analysis. Our theory treats memory random-access latency, and its cost per installed mega...
IPPS
1994
IEEE
14 years 21 days ago
1994
IEEE
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
CCGRID
2003
IEEE
14 years 1 months ago
2003
IEEE
Increasingly large-scale clusters of PC/WS continue to become majority platform in HPC field. Such a commodity cluster environment, there may be incremental upgrade due to severa...
TC
2010
13 years 3 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...