2204 search results - page 57 / 441 » Analyzing architectural styles |
133
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ISLPED
2004
ACM
15 years 9 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
166
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FPGA
2001
ACM
15 years 8 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
128
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FPGA
2006
ACM
15 years 7 months ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
213
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WWW
2011
ACM
14 years 11 months ago
2011
ACM
The advent of Cloud computing platforms, and the growing pervasiveness of Multicore processor architectures have revealed the inadequateness of traditional programming models base...
150
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NOCS
2009
IEEE
15 years 10 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...