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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 2 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
HPCA
1995
IEEE
14 years 1 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
ISEMANTICS
2010
13 years 11 months ago
Twarql: tapping into the wisdom of the crowd
Twarql is an infrastructure translating microblog posts from Twitter as Linked Open Data in real-time. The approach employed in Twarql can be summarized as follows: (1) extract co...
Pablo N. Mendes, Alexandre Passant, Pavan Kapanipa...
CONCURRENCY
2007
95views more  CONCURRENCY 2007»
13 years 10 months ago
Automated and accurate cache behavior analysis for codes with irregular access patterns
Abstract. The memory hierarchy plays an essential role in the performance of current computers, thus good analysis tools that help predict and understand its behavior are required....
Diego Andrade, Manuel Arenaz, Basilio B. Fraguela,...
SIGMETRICS
2010
ACM
213views Hardware» more  SIGMETRICS 2010»
14 years 2 months ago
Small subset queries and bloom filters using ternary associative memories, with applications
Associative memories offer high levels of parallelism in matching a query against stored entries. We design and analyze an architecture which uses a single lookup into a Ternary C...
Ashish Goel, Pankaj Gupta