Sciweavers

7167 search results - page 1322 / 1434
» Answer Set Programming
Sort
View
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 3 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
RTSS
2006
IEEE
14 years 3 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 3 months ago
A robust detailed placement for mixed-size IC designs
— The rapid increase in IC design complexity and wide-spread use of intellectual-property (IP) blocks have made the so-called mixed-size placement a very important topic in recen...
Jason Cong, Min Xie
CVPR
2010
IEEE
14 years 2 months ago
Semantic Context Modeling with Maximal Margin Conditional Random Fields for Automatic Image Annotation
Context modeling for Vision Recognition and Automatic Image Annotation (AIA) has attracted increasing attentions in recent years. For various contextual information and resources,...
Yu Xiang, Xiangdong Zhou, Zuotao Liu, Tat-seng chu...
CGO
2005
IEEE
14 years 2 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
« Prev « First page 1322 / 1434 Last » Next »