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IPPS
2006
IEEE
14 years 2 months ago
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
IJPP
2006
145views more  IJPP 2006»
13 years 8 months ago
Deterministic Parallel Processing
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
Gajinder Panesar, Daniel Towner, Andrew Duller, Al...
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
14 years 1 months ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
ICPPW
2006
IEEE
14 years 2 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills
RTCSA
2009
IEEE
14 years 3 months ago
Towards Hardware Support for Common Sensor Processing Tasks
—Sensor processing is a common task within many embedded system domains, such as in control systems, the sensor feedback is used for actuator control. In this paper we have surve...
Adwait Gupte, Phillip Jones