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ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
14 years 22 days ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 7 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
HPDC
2000
IEEE
13 years 12 months ago
Failure-Atomic File Access in an Interposed Network Storage System
This paper presents a recovery protocol for block I/O operations in Slice, a storage system architecture for highspeed LANs incorporating network-attached block storage. The goal ...
Darrell C. Anderson, Jeffrey S. Chase
ASPLOS
2004
ACM
14 years 28 days ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
APPT
2009
Springer
14 years 2 months ago
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices
SIMD extension is one of the most common and effective technique to exploit data-level parallelism in today’s processor designs. However, the performance of SIMD architectures i...
Asadollah Shahbahrami, Ben H. H. Juurlink