86 search results - page 4 / 18 » Application-Specific Computing with Adaptive Register File A... |
IEEEPACT
2002
IEEE
14 years 12 days ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
HIPC
2003
Springer
14 years 20 days ago
2003
Springer
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. A...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes the outcomes of the NSF Grant CNS-0615085: CSR-EHS: Enhancing the Effectiveness of Utilizing an Instruction Register File. We improved promoting instructions ...