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109
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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
15 years 8 months ago
Enabling efficient post-silicon debug by clustering of hardware-assertions
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
Mohammad Hossein Neishaburi, Zeljko Zilic
116
Voted
DELTA
2002
IEEE
15 years 7 months ago
European Network for Test Education
 The European network for Integrated Circuit testing education described in this paper addresses the shortage of skill in mixed-signal production testing by encouraging students...
Yves Bertrand, Marie-Lise Flottes, Florence Aza&iu...
157
Voted
DAC
1997
ACM
15 years 7 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
137
Voted
ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
15 years 7 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
127
Voted
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
15 years 7 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer