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ITC
1996
IEEE
114views Hardware» more  ITC 1996»
13 years 12 months ago
A Demonstration IC for the P1149.4 Mixed-Signal Test Standard
The P1149.4 mixed-signal boundary scan standard is demonstrated with a CMOS integrated circuit. Design issues and characterization data are presented.
Keith Lofstrom
CLEIEJ
2010
13 years 5 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
INTEGRATION
2008
94views more  INTEGRATION 2008»
13 years 7 months ago
Variability in nanometer CMOS: Impact, analysis, and minimization
Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this paper, we review...
Dennis Sylvester, Kanak Agarwal, Saumil Shah
SLIP
2009
ACM
14 years 2 months ago
From 3D circuit technologies and data structures to interconnect prediction
New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
Robert Fischbach, Jens Lienig, Tilo Meister
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
14 years 2 months ago
Multi-Vth Level Conversion Circuits for Multi-VDD Systems
— Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfe...
Sherif A. Tawfik, Volkan Kursun