We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubn...
This paper focuses on the investigation of integrated CMOS and Silicon/Germanium (SiGe) devices for highspeed optical receiver circuits. In this paper, we present several competit...
Amit Gupta, Steven P. Levitan, Leo Selavo, Donald ...