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CHES
2005
Springer
100views Cryptology» more  CHES 2005»
14 years 1 months ago
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
Thomas Popp, Stefan Mangard
FPL
2005
Springer
115views Hardware» more  FPL 2005»
14 years 1 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
ISNN
2005
Springer
14 years 1 months ago
A Novel Solid Neuron-Network Chip Based on Both Biological and Artificial Neural Network Theories
Built on the theories of biological neural network, artificial neural network methods have shown many significant advantages. However, the memory space in an artificial neural chip...
Zihong Liu, Zhihua Wang, Guolin Li, Zhiping Yu
ARCS
2004
Springer
14 years 1 months ago
Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras
: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for in...
Dietmar Fey, Daniel Schmidt 0003, Andreas Loos
FPL
2004
Springer
103views Hardware» more  FPL 2004»
14 years 1 months ago
JHDLBits: The Merging of Two Worlds
Abstract. This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits wi...
Alexandra Poetter, Jesse Hunter, Cameron Patterson...