A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated CAD problems have gained much attention, most of which has been devoted to d...
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang...
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Air cooling limits have been a major design challenge in recent years for integrated circuits. Multi-core exacerbates thermal challenges because power scales with the number of co...
Wei Huang, Mircea R. Stan, Karthik Sankaranarayana...