Driver waveform computation for timing analysis with multiple voltage threshold driver models

This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs formalize a class of gate models which include the existing industry standards, such as CCS and ECSM driver models as special cases. The analysis technique relies on primary MVTM characterization data and does not require explicit instantiation of controlled current source models. Therefore, the method is more accurate, efficient, and general than traditional transient analysis. The theoretical results are validated by detailed simulations and use within full chip timing analysis. Categories and Subject Descriptors B.7 [INTEGRATED CIRCUITS]: Design Aids General Terms Algorithms Keywords Current Source Model, Effective Capacitance

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta
• Keywords: Current Source Models, DAC 2008, Design Automation, Efficient Electrical Analysis, Voltage Threshold Models