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    ISPD
    2005
    ACM
    116views Hardware» more  ISPD 2005»
    A fast algorithm for power grid design
    14 years 1 months ago
    A fast algorithm for power grid design
    Download  www.ece.umn.edu
    This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
    Jaskirat Singh, Sachin S. Sapatnekar
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    SBCCI
    2005
    ACM
    111views VLSI» more  SBCCI 2005»
    Total leakage power optimization with improved mixed gates
    14 years 1 months ago
    Total leakage power optimization with improved mixed gates
    Download  www.cpdee.ufmg.br
    Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
    Frank Sill, Frank Grassert, Dirk Timmermann
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    SLIP
    2005
    ACM
    248views Computer Networks» more  SLIP 2005»
    A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
    14 years 1 months ago
    A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
    Download  mtlweb.mit.edu
    The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
    Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
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    CHES
    2005
    Springer
    109views Cryptology» more  CHES 2005»
    Security Evaluation Against Electromagnetic Analysis at Design Time
    14 years 1 months ago
    Security Evaluation Against Electromagnetic Analysis at Design Time
    Download  www.cl.cam.ac.uk
    Electromagnetic analysis (EMA) can be used to compromise secret information by analysing the electric and/or magnetic fields emanating from a device. It follows differential power...
    Huiyun Li, A. Theodore Markettos, Simon W. Moore
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    FPGA
    2005
    ACM
    156views FPGA» more  FPGA 2005»
    Design of programmable interconnect for sublithographic programmable logic arrays
    14 years 1 months ago
    Design of programmable interconnect for sublithographic programmable logic arrays
    Download  ic.ese.upenn.edu
    Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
    André DeHon
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