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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 13 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
DAC
2010
ACM
14 years 4 days ago
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement
Carbon Nanotubes (CNTs) are grown using chemical synthesis, and the exact positioning and chirality of CNTs are very difficult to control. As a result, “small-width” Carbon Na...
Jie Zhang, Shashikanth Bobba, Nishant Patil, Alber...
JOCN
2010
68views more  JOCN 2010»
13 years 6 months ago
Shared Neural Circuits for Mentalizing about the Self and Others
■ Although many examples exist for shared neural representations of self and other, it is unknown how such shared representations interact with the rest of the brain. Furthermor...
Michael V. Lombardo, Bhismadev Chakrabarti, Edward...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
DT
2002
67views more  DT 2002»
13 years 8 months ago
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors
This article presents an in-circuit emulation (ICE) module that can be embedded with a microprocessr core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typ...
Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching...