Sciweavers

259 search results - page 26 / 52
» Application-specific instruction generation for configurable...
Sort
View
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
14 years 7 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
IEEEPACT
2000
IEEE
13 years 11 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 7 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
13 years 11 months ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...
DAC
2009
ACM
14 years 8 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong