Sciweavers

259 search results - page 27 / 52
» Application-specific instruction generation for configurable...
Sort
View
DAC
2007
ACM
14 years 8 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
DAC
1999
ACM
14 years 8 months ago
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
JSA
2000
116views more  JSA 2000»
13 years 7 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
ASAP
2003
IEEE
124views Hardware» more  ASAP 2003»
14 years 21 days ago
Arbitrary Bit Permutations in One or Two Cycles
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
Zhijie Shi, Xiao Yang, Ruby B. Lee