Sciweavers

3256 search results - page 3 / 652
» Applications of Formal Methods to System Design and Verifica...
Sort
View
HASE
2008
IEEE
13 years 7 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 11 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
CCECE
2006
IEEE
14 years 1 months ago
A Formal CSP Framework for Message-Passing HPC Programming
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
John D. Carter, William B. Gardner
ICMCS
2006
IEEE
119views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Design and Verification of Communication Protocols for Peer-to-Peer Multimedia Systems
This paper addresses issues pertaining to the necessity of utilizing formal verification methods in the design of protocols for peer-to-peer multimedia systems. These systems req...
Senem Velipasalar, Chang Hong Lin, Jason Schlessma...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler