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FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 27 days ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
ICCS
2003
Springer
14 years 26 days ago
Generalization of the Fast Consistency Algorithm to a Grid with Multiple High Demand Zones
Abstract. One of the main challenges of grid systems of large scale and data intensive is that of providing high availability and performance, in spite of the unreliability and del...
Jesús Acosta-Elías, Leandro Navarro-...
ISVLSI
2002
IEEE
89views VLSI» more  ISVLSI 2002»
14 years 18 days ago
Speedup of Self-Timed Digital Systems Using Early Completion
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
Scott C. Smith
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
14 years 1 days ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 11 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...