This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
Abstract. One of the main challenges of grid systems of large scale and data intensive is that of providing high availability and performance, in spite of the unreliability and del...
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...