Sciweavers

52 search results - page 8 / 11
» Applying Interposition Techniques for Performance Analysis o...
Sort
View
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 8 days ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
RSA
2000
170views more  RSA 2000»
13 years 6 months ago
Delayed path coupling and generating random permutations
We analyze various stochastic processes for generating permutations almost uniformly at random in distributed and parallel systems. All our protocols are simple, elegant and are b...
Artur Czumaj, Miroslaw Kutylowski
MIDDLEWARE
2007
Springer
14 years 25 days ago
Dynamic multi-process information flow tracking for web application security
Although there is a large body of research on detection and prevention of such memory corruption attacks as buffer overflow, integer overflow, and format string attacks, the web...
Susanta Nanda, Lap-Chung Lam, Tzi-cker Chiueh
HPCA
2003
IEEE
14 years 7 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
JRTIP
2008
249views more  JRTIP 2008»
13 years 6 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...