62 search results - page 12 / 13 » Applying Logic Synthesis for Speeding Up SAT |
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, ...
ATAL
2000
Springer
14 years 8 days ago
2000
Springer
In this paper we propose a methodology to help analyse tendencies in MAS to complement those of simple inspection, Monte Carlo and syntactic proof. We suggest an architecture that ...
FORMATS
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Introducing a monitor on a system typically changes the system's behaviour by slowing the system down and increasing memory consumption. This may possibly result in ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...