Sciweavers

62 search results - page 6 / 13
» Applying Logic Synthesis for Speeding Up SAT
Sort
View
TCAD
1998
126views more  TCAD 1998»
13 years 7 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli
DAC
1999
ACM
14 years 8 days ago
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
Priyadarshan Patra, Unni Narayanan
CL
2000
Springer
14 years 9 days ago
Modelling Digital Circuits Problems with Set Constraints
A number of diagnostic and optimisation problems in Electronics Computer Aided Design have usually been handled either by specific tools or by mapping them into a general problem s...
Francisco Azevedo, Pedro Barahona
MEMOCODE
2007
IEEE
14 years 2 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 8 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco