Sciweavers

41 search results - page 3 / 9
» Approximate Time-Parallel Cache Simulation
Sort
View
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
WWW
2003
ACM
14 years 8 months ago
Scalable techniques for memory-efficient CDN simulations
Since CDN simulations are known to be highly memory-intensive, in this paper, we argue the need for reducing the memory requirements of such simulations. We propose a novel memory...
Purushottam Kulkarni, Prashant J. Shenoy, Weibo Go...
DATE
2008
IEEE
155views Hardware» more  DATE 2008»
14 years 1 months ago
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems
The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work...
Pierre Guironnet de Massas, Frédéric...
ASPLOS
2009
ACM
14 years 8 months ago
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
David K. Tam, Reza Azimi, Livio Soares, Michael St...
PAM
2004
Springer
14 years 21 days ago
Measurements and Laboratory Simulations of the Upper DNS Hierarchy
Given that the global DNS system, especially at the higher root and top-levels, experiences significant query loads, we seek to answer the following questions: (1) How does the ch...
Duane Wessels, Marina Fomenkov, Nevil Brownlee, Ki...