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» Approximate logic synthesis for error tolerant applications
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GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
14 years 28 days ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
14 years 2 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
EDCC
2006
Springer
14 years 6 days ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
IOLTS
2003
IEEE
126views Hardware» more  IOLTS 2003»
14 years 1 months ago
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...
CIBCB
2007
IEEE
14 years 2 months ago
Multiple Sequence Alignment using Fuzzy Logic
—DNA matching is a crucial step in sequence alignment. Since sequence alignment is an approximate matching process there is a need for good approximate algorithms. The process of...
Sara Nasser, Gregory Vert, Monica N. Nicolescu, Al...