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ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato

Publication
196views
15 years 6 months ago
Improving the Performance of TCP over the ATM-UBR service
In this paper we study the design issues in improving TCP performance over the ATM UBR service. ATM-UBR switches respond to congestion by dropping cells when their buffers become f...
Rohit Goyal, Raj Jain, Shiv Kalyanaraman, Sonia Fa...
LISA
2007
13 years 10 months ago
Application Buffer-Cache Management for Performance: Running the World's Largest MRTG
An operating system’s readahead and buffer-cache behaviors can significantly impact application performance; most often these better performance, but occasionally they worsen it...
David Plonka, Archit Gupta, Dale Carder
HPCA
2005
IEEE
14 years 8 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
13 years 11 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler