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RTAS
1997
IEEE
14 years 1 days ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 1 months ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck
ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
11 years 10 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
14 years 1 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
WSC
2000
13 years 9 months ago
Virtual machines for message based, real-time and interactive simulation
An advanced processing machine interacts with the material handling system, personnel and cell or shop floor controller in real-time via messaging and control. However, current si...
Hansoo Kim, Chen Zhou, Hua X. Du