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» Architectural Considerations for Energy Efficiency
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OSDI
2008
ACM
14 years 8 months ago
Memory-aware Scheduling for Energy Efficiency on Multicore Processors
Memory bandwidth is a scarce resource in multicore systems. Scheduling has a dramatic impact on the delay introduced by memory contention, but also on the effectiveness of frequen...
Andreas Merkel, Frank Bellosa
MOBIHOC
2008
ACM
14 years 8 months ago
Towards energy efficient VoIP over wireless LANs
Wireless LAN (WLAN) radios conserve energy by staying in sleep mode. With real-time applications like VoIP, it is not clear how much energy can be saved by this approach since pac...
Vinod Namboodiri, Lixin Gao
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 12 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
DAC
1997
ACM
13 years 12 months ago
Low Energy Memory and Register Allocation Using Network Flow
This paper presents for the first time low energy simultaneous memory and register allocation. A minimum cost network flow approach is used to efficiently solve for minimum energy...
Catherine H. Gebotys
FPL
2005
Springer
73views Hardware» more  FPL 2005»
14 years 1 months ago
Energy-Efficient NoC for Best-Effort Communication
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energ...
Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Bec...